In the process of manufacturing a package containing an embedded semiconductor die, undesirably low device yield can occur due to the processing methodology. For example, an embedded device panel comprises one or more semiconductor dies and an encapsulant. The encapsulant surrounds the one or more semiconductor dies on at least three side surfaces of each semiconductor die, with at least an active side of the one or more semiconductor dies exposed for further processing. During manufacturing, high temperature processes and materials mismatch between the encapsulant, semiconductor dies, and build-up layers, and encapsulant shrinkage can cause the panel to warp.
Due to warping of the panel, a number of problems can occur. For example, an excessively warped panel cannot be processed on high speed fully automated handling equipment, which also includes integrated inspection and package pick and placement. The warped panel cannot be processed on such handling equipment due to an inability to attain a reliable vacuum using a conventional tape-less support structure, sometimes referred to as a tape-less contact chuck. In particular, it is difficult to maintain an airtight seal between an excessively warped panel and the tape-less contact chuck. Thus, vacuum can be lost and the panel, or a portion of the panel, can dislodge from the chuck and become damaged from contact with external surfaces. Consequently, an alternative and, typically more costly, process flow may be called for to handle the warped panels. Such a process flow may entail dicing, or singularizing, the panel on tape, followed by picking the singularized semiconductor devices from the tape, and placing the devices into carriers using a different equipment set.
Some semiconductor device designs call for fine pitch land grid array (LGA), which require solder pre-tinning. Solder pre-tinning is typically performed by implementing stencil printing and reflow techniques while the panel is held onto a tape-less chuck through the application of a vacuum. However, for some large array panels, the warp is so severe that a sufficient vacuum to support the stencil process cannot be attained. In addition, consistent spacing between the warped substrate, i.e., panel, and the stencil is not possible. Consequently, inconsistent solder paste application may occur, again contributing to a decrease in yield. An alternative process flow may be to singularize the semiconductor devices first, followed by solder pre-tinning. Such a process may be viable but is highly inefficient.
The risk for warp of the panel, or substrate, is especially high in a prototype environment where non-fully populated panels, material changes, or short flows are necessary for quick cycles of learning. In addition, warp is becoming increasingly difficult to control in a full production environment as panel size is increased and/or as panel thickness is reduced.